1. Field of the Invention
This invention relates to non-volatile semiconductor memory and to circuits and processes for writing threshold voltages in memories, particularly multi-bit-per-cell memories.
2. Description of Related Art
Most known multi-bit-per-cell non-volatile memory integrated circuits have memory cells that include floating gate devices such as floating gate or split gate transistors. Each floating gate device has a programmable threshold voltage in a range that is divided into multiple intervals with each interval corresponding to a different multibit value. To write a particular multibit value in a memory cell, the threshold voltage of the floating gate device in the memory cell is precisely programmed into the threshold voltage interval that corresponds to the value. Accordingly, write methods for precisely programming threshold voltages have been developed, but such write methods can be slow. Accordingly, the write speed can limit the data bandwidth for a multi-bit-per-cell memory. Similar bandwidth limitations arise in analog/multi-level non-volatile memory where a write operation must set the threshold voltage of a memory cell precisely to a level that corresponds to an analog/multi-level value being written.
One way to increase the data bandwidth for programming is to include in an integrated circuit memory, multiple memory arrays or banks that operate in parallel or pipeline fashion. For example, U.S. Pat. No. 5,680,341, entitled "Pipelined Record and Playback for Analog Non-Volatile Memory", which is hereby incorporated by reference in its entirety, describes known analog memory systems using pipelined write operations for high data bandwidth. FIG. 1 is a block diagram of a non-volatile memory 100 including multiple write pipelines 110 for pipelined write operations. Each write pipeline 110 includes an array 130 of memory cells and a write circuit 120 that couples to a row decoder 132 and a column decoder 134 for the associated array 130. Pipelines 110 operate independently to complete separate programming operations that a timing circuit 140 sequentially starts. As a result, N pipelines 110 simultaneously perform different stages of up to N write operations for writing up to N different data values from a data source 110. The number N of pipelines 110 in memory 100 determines the maximum number of simultaneous write operations memory 100 and accordingly controls the maximum data bandwidth for writing to memory 100.
The improved data bandwidth of memory 100 comes at the cost of increased circuit complexity. In particular, each write pipeline 110 includes a separate write circuit 120. Write circuits for multi-bit-per-cell and/or analog memories and can be complex, and the redundant use of the write circuits increases required integrated circuit area and the costs of high bandwidth multi-bit-per-cell and analog/multi-level memories.